IBIS Macromodel Task Group Meeting date: 06 Sep 2011 Members (asterisk for those attending): Agilent: Fangyi Rao * Radek Biernacki Altera: * David Banas Ansys: Samuel Mertens * Dan Dvorscak * Curtis Clark Arrow Electronics: Ian Dodd Cadence Design Systems: Terry Jernberg * Ambrish Varma Celsionix: Kellee Crisafulli Cisco Systems: Ashwin Vasudevan Syed Huq Ericsson: Anders Ekholm IBM: * Greg Edlund Intel: Michael Mirmak LSI Logic: Wenyi Jin Mentor Graphics: * John Angulo Zhen Mu * Arpad Muranyi Vladimir Dmitriev-Zdorov Micron Technology: Randy Wolff NetLogic Microsystems: Ryan Couts Nokia-Siemens Networks: * Eckhard Lenski QLogic Corp. * James Zhou Sigrity: Brad Brim * Kumar Keshavan * Ken Willis SiSoft: * Walter Katz * Todd Westerhoff Doug Burns Snowbush IP: Marcus Van Ierssel ST Micro: Syed Sadeghi Teraspeed Consulting Group: Scott McMorrow * Bob Ross TI: Casey Morrison Alfred Chong Vitesse Semiconductor: Eric Sweetman Xilinx: Mustansir Fanaswalla unaffiliated: * Mike LaBonte The meeting was lead by Arpad Muranyi ------------------------------------------------------------------------ Opens: - Arpad: Last week we discussed having an IBIS section on version differences - Walter: IBIS 5.1 should only discuss AMI 5.1 - We should take a resolution to the Open Forum - Arpad: We should have this on the agenda - Greg Edlund wanted to show some slides on jitter -------------------------- Call for patent disclosure: - None ------------- Review of ARs: - Arpad: Inform Open Forum that BIRDs 137.1 and 143 will not change - In progress - Fangyi: to send suggestions on Jitter BIRD to Walter - Done - Walter: Send updated BIRDs 123.2.4 to Mike for posting - Was sent to list AR: Mike post latest BIRD 123.2.3 to ATM web ------------- New Discussion: Arpad showed BIRD 137.2: - One minor typographical fix - Arpad described the changes - Bob: This is ready to go - There should be discussion on how we deal with version changes - Walter motioned to submit the BIRD to Open Forum - Curtis seconded AR: Arpad submit BIRD 137.2 to Open Forum Arpad showed BIRD 143.1: - This has the same changes as BIRD 137.2 - Arpad described the changes - Walter motioned to submit the BIRD to Open Forum - Curtis seconded AR: Arpad submit BIRD 143.1 to Open Forum Arpad showed BIRD 140.1: - Arpad: This has new wording that Walter and I agreed to - [External Model] and [External Circuit] have "corner_name" - We only need to reference these names (Typ, Min, Max) - This could have another paragraph about dependency tables - We are not yet ready for that in this BIRD - AMI have have to map to those names to 0, 1, 2 - Walter: EDA tools all have an intrinsic corner variable - In one place Corner is a Format - In another it's a parameter - Bob: For Type String Corner would be quoted - Walter described a Corner parameter - Arpad: The question is if we want to untable this BIRD - We can discuss next meeting - Walter motioned to discuss BIRD 140.1 next meeting - Bob and David seconded - Ambrish asked if we should wait for dependency tables first Arpad showed a slide presentation from Greg: - Greg: Have been discussing AMY issues in Quality task group meetings - Have been doing jab work to verify models - Studying where jitter comes from - Users will see a list of parameters but will not know know what they are controlling - BIRD 123 are jitter terms external to the DLL - Walter; Rx_Noise is an exception - Todd: That is still external to the DLL - Slide 1: - Greg explain the diagram - Walter: The analog model is dashed - The PKG is in there but it's usually in the IBIS file - EQ may be between Pre and Out - Greg: A 1 tap would have 2 parallel output stages - Walter: That depends on how the TX is implemented - Todd: EQ should be before Pre - Walter: Replace Pre with EQ - Todd: - Arpad: What is the purpose of the Quality discussion? - Greg: What does the DLL correspond to? - Walter: The Pre - Arpad changed Pre to EQ - Todd: Jitter is only what comes out of the EQ box - Ambrish: So no jitter can be in the model? - Walter: It can't be in Init - If it is Getwave the EDA tool must not add more jitter - The refclk path is controlled by AVDD and VDD - David: Can we tell the DLL what noise to assume? - Walter: We have params to tell the EDA tool what the DLL models - Todd: The block marked AMI should be Algorithmic - Radek: The pkg is not part of the model? - Walter: It is in IBIS - Arpad: Those are often not good enough - Ambrish: Will PKG affect IR? - Todd: yes - David: For FPGAs the PKG has to be kept separable - Radek: The PKG is to be used if it is in the IBIS file - Arpad made further block diagram changes The call dropped saying that the chairperson disconnected. We resumed: - Todd: When we say "model" it means to the edge of the die -The analog channel includes all interconnect - Walter: It also includes Term - James: Where is the analog data saved? - Walter: We know where the PKG and ALG models are - The buffer analog in 5.0 is either IV/VT or [External Model] - BIRD 122 proposes new AMI parameters to describe intrinsic models - It will be something like a Thevenin or Touchstone model - It might be ISS at some point - The jitter could be internal or external to the AMI file - James: Model makers have to provide TX DCD, etc.? - Kumar: They only have to give corner values - Walter: Model makers will know what jitter params are and are not included - The ones not included must be parameters - Radek: Users can not modify that - Todd: If jitter is a range it implies the user can pick a number - James: So users can change model jitter parameters? - Walter: Users can select jitter if the model allows it - Todd: Should users change AMI files? - Kumar: Users do not have unlimited freedom to change AMI files? - Walter: If IP is placed in different ICs the jitter changes - James: The model maker can't know what the power supply is like - Ambrish: Some jitter comes from the system - The EDA tool has to add that - Can the user add more DCD? - Walter: Yes - We should remove Out as an option for jitter params - Kumar: If the AMI gives a range how will the user know he can add more jitter? - Walter: The manual should give enough info - Todd: The proposal is for the EDA tool to modulate stimulus - The DLL can modify internally - It can have an AMI that sets jitter to zero - Users can edit that file - Ambrish: What does the user do the add more system jitter - Todd: If users do not edit AMI files the value can be a corner or range - The EDA tool can still prompt for additional jitter - James: The spec and EDA tool can do many things - It's hard to know what it is actually doing though - Todd: They may have trade secrets - James: I need to know what is in and not in the model - Todd: Anything handled by the DLL should be zero in the AMI file - Walter: There will be a PS component that will be low frequency - The EDA tool has to account for that - James: Can we tell the user which parameters not to change? - Walter: They should not change AMI files - Ambrish: The EDA tool could handle it internally - Todd: We have a model standard for ICs - We can't tell and EDA tool what it can't do - Greg: The DLL would have to model refclk jitter - Walter: The DLL does not handle that - It gets transition times - Todd: It is modifying the output - James: Walter was saying the opposite - Walter: Transition times will have any jitter added by the tool - Todd: Nothing on the table now talks about that refclk input - Greg: This was an issue in the early days of PCIe - Walter: They gave budgets for jitter at the output - There was nothing at the inputs - Now they have to describe jitter propagation - It can't be a compliance test any more - James: It is still not clear what the DLL is not doing - Walter: It would be appropriate for the DLL to say what it's input should include - Ambrish: These models are supposed to be black box - Todd: We can standardize how jitter is injected - Models can be made with parameters that together model all jitter - James: It should be clear that these jitter params do not mean the model handles it - Even for Rj - Walter: There is a debate about Rj - Applying it in time domain up front will not be accurate enough to get the tails - Post-processing may be better - Walter read from BIRD 123 to clarify this Slide 2 was not discussed Meeting ended. ------------- Next meeting: 6 Sep 2011 12:00pm PT Next agenda: 1) Task list item discussions ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives